/*******************************************************************************

    COPYRIGHT (C) LAB601, Southeast University
    ----------------------------------------
    File Name:      pci_behavior.v
    Title:          PCI Behavior Top
    Author:         Len D.
    Email:          neldon@gmail.com
    Revision:       0.8
    Date:           2009-11-10
    Description:    1) PCI behavior top module.
                    2) Include behavior models.
    Other:          //
    ----------------------------------------
    History
    ----------
    Date        By          Description
    ----------  ----------  --------------------------------------------------
    2008-11-10  Len D.      a) Initialized.
    
*******************************************************************************/
module PCI_BEHAVIOR(
                    pciclk,
                    rst_n,
                    frame_n,
                    irdy_n,
                    devsel_n,
                    trdy_n,
                    stop_n,
                    serr_n,
                    ad,
                    cbe_n,
                    par,
                    perr_n,
                    req_n,
                    gnt_n,
                    inta_n
                    );
    // ports.
    output pciclk;              // PCI Clock.
    input  rst_n;
    inout  frame_n;             // PCI Cycle Frame.
    inout  irdy_n;              // Initiator Ready.
    inout  devsel_n;            // PCI Device Select.
    inout  trdy_n;              // Target Ready.
    inout  stop_n;              // PCI Bus Stop.
    input  serr_n;              // System Error.
    inout  [31:0] ad;           // PCI Address / Data Bus.
    inout  [3:0]  cbe_n;        // PCI Command / Byte Enables.
    inout  par;                 // PCI Bus Parity.
    inout  perr_n;              // PCI Request From Conntroller.
    input  req_n;               // PCI Bus Request.
    output gnt_n;               // PCI Bus Grant.
    inout  inta_n;              // 
    
    // wires.
    wire disengage_mstr;        // master -> monitor.
    wire tranx_success;         // master -> monitor.
    wire trgt_tranx_disca;      // master -> target.
    wire trgt_tranx_discb;      // master -> target.
    wire trgt_tranx_retry;      // master -> target.
    wire busfree;               // arbiter -> master.
    wire mstr_tranx_gnt_n;
    wire mstr_tranx_req_n;
    wire [1:0] reqns;           // bus -> arbiter.
    wire [1:0] gntns;           // arbiter -> bus.
    

    // wire logic.
    assign {mstr_tranx_gnt_n, gnt_n} = gntns;
    assign reqns = {mstr_tranx_req_n, req_n};

    // clk generator
    // src/behavior/pci_behavior/clk_gen.v
    clk_gen inst_clk_gen(
                        .pciclk (pciclk     )
                        );

    // pull up
    // src/behavior/pci_behavior/pull_up.v
    pull_up inst_pull_up(
                        .ad     (ad         ),
                        .cben   (cbe_n      ),
                        .par    (par        ),
                        .framen (frame_n    ),
                        .irdyn  (irdy_n     ),
                        .devseln(devsel_n   ),
                        .trdyn  (trdy_n     ),
                        .stopn  (stop_n     ),
                        .perrn  (perr_n     ),
                        .serrn  (serr_n     ),
                        .intan  (inta_n     )
                        );

    // pci bus arbiter
    // src/behavior/pci_behavior/arbiter.v
    arbiter inst_arbiter(
                        .clk    (pciclk     ),
                        .rstn   (rst_n      ),
                        .busfree(busfree    ),
                        .pci_reqn   (reqns  ),
                        .pci_gntn   (gntns  )
                        );
    
    // master transmitt
    // src/behavior/pci_behavior/mstr_tranx.v
    mstr_tranx inst_master_tx (
                   .clk     (pciclk     ),
                   .rstn    (rst_n      ),
                   .ad      (ad         ),
                   .cben    (cbe_n      ),
                   .par     (par        ),
                   .reqn    (mstr_tranx_req_n   ),
                   .gntn    (mstr_tranx_gnt_n   ),
                   .framen  (frame_n    ),
                   .irdyn   (irdy_n     ),
                   .devseln (devsel_n   ),
                   .trdyn   (trdy_n     ),
                   .stopn   (stop_n     ),
                   .perrn   (perr_n     ),
                   .serrn   (serr_n     ),
                   .busfree (busfree    ),
                   .disengage_mstr  (disengage_mstr ),
                   .tranx_success   (tranx_success  ),
                   .trgt_tranx_disca(trgt_tranx_disca),
                   .trgt_tranx_discb(trgt_tranx_discb),
                   .trgt_tranx_retry(trgt_tranx_retry)
                   );

    // target transmitt
    // src/behavior/pci_behavior/trgt_tranx.v
    trgt_tranx inst_target_tx (
                   .clk     (pciclk     ),
                   .rstn    (rst_n      ),
                   .ad      (ad         ),
                   .cben    (cbe_n      ),
                   .idsel   (ad[29]     ),
                   .par     (par        ),
                   .framen  (frame_n    ),
                   .irdyn   (irdy_n     ),
                   .devseln (devsel_n   ),
                   .stopn   (stop_n     ),
                   .trdyn   (trdy_n     ),
                   .perrn   (perr_n     ),
                   .serrn   (serr_n     ),
                   .trgt_tranx_disca(trgt_tranx_disca),
                   .trgt_tranx_discb(trgt_tranx_discb),
                   .trgt_tranx_retry(trgt_tranx_retry)
                   );

    // pci bus monitor
    // moved to PCI7600_monitor.v
endmodule
